`timescale 10ns/1ps

module MUX_2to1_test;

	reg [4:0] D0, D1;
	reg S0;
	wire [4:0] Y;
	
	
	MUX_2to1 #(5) U0 (.*);

	initial
	fork
		{D0, D1} <= 10'b00110_10101;
		S0 <= 1'b0;
		#10 S0 <= 1'b1;
	join
endmodule